Abstract
A simple large signal model allowing first hand sizing of low power analog MOS circuits is desirable. Unfortunately, there aren't many candidates.
The classical quadratic model takes no notice of weak and moderate inversion. It ignores short channel effects and is unable moreover to predict output impedances. Advanced models that take these into consideration are currently implemented in modern simulators, like SPICE, BSIM or PSP. However, aside from verifications based on reiterated simulations, none lends itself to circuit design owing to the huge numbers of parameters and equations they require.
The basic E.K.V. model presents an interesting exception. It is simple, takes all modes of operation of MOS transistors into consideration and features an interesting attribute. Once the source and drain voltages are fixed, weak and moderate inversion drain currents can be predicted with an accuracy of a few per cent over more than seven decades. Only three parameters are required therefore, even with submicron transistors. The parameters can be extracted from the models available in the advanced simulators.
Being a surrogate of the well-known Charge Sheet Model (C.S.M), the E.K.V. model suffers from the same insufficiencies. However, it does not mimic the output impedance of saturated transistors, nor does it take into account short channel effects. The changes the parameters undergo when the drain (or source) voltage is modified bear witness nevertheless not only of short channel effects, but take in also output impedances. The dependence on bias conditions can be put to use in order to evaluate gain for instance.
A number of examples are reviewed illustrating the potential and promises of the basic E.K.V.1 model for low-power design. How it paves the way towards sizing through the evaluation of the gm/ID ratio is shown.
About the speaker
Prof Paul Jespers received his PhD Applied Sciences from the Université Catholique de Louvain (UCL) and founded the microelectronics section in the 1960’s. He was an invited guest at Stanford University and a visiting professor at the University of California at Berkeley, in 1968 and 1991 respectively. He lectured in several Institutions in South America, China, India and Australia. He is currently an Emeritus Professor at UCL.
In the 1980’s, Prof Jespers fulfilled a C.T.A. assignment for the United Nations Industrial Development Organization in India. His interests relate to analog CMOS circuits with emphasis of converters and sizing methodologies. He is the co-inventor of the charge-pumping effect and co-author of the first gm/ID paper.
Prof Jespers is a former member of the IEEE Solid State Council and the Steering Committee of ESSDERC - ESSCIRC. He is a Life Fellow of the IEEE.
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